97 search results - page 4 / 20 » Design and implementation of JPEG encoder IP core |
VLSISP
2011
13 years 2 months ago
2011
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
JCM
2008
13 years 7 months ago
2008
With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the perf...
MSE
2003
IEEE
14 years 19 days ago
2003
IEEE
The increasing gap between design productivity and chip complexity, and emerging systems-on-a-chip (SoC) have led to the wide utilization of reusable intellectual property (IP) co...
ISCAS
2003
IEEE
14 years 19 days ago
2003
IEEE
MPEG-4 Fine Granularity Scalability (FGS) provides bandwidth adaptation and error resilience features for streaming applications. In this paper. by estimating the required computa...
ERSA
2006
13 years 8 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...