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» Design considerations for MRAM
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DAC
2009
ACM
15 years 11 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ICASSP
2009
IEEE
15 years 11 months ago
Scalable distributed source coding
This paper considers the problem of scalable distributed coding of correlated sources that are communicated to a central unit. The general setting is typically encountered in sens...
Ankur Saxena, Kenneth Rose
IJCNN
2008
IEEE
15 years 10 months ago
Evolving a neural network using dyadic connections
—Since machine learning has become a tool to make more efficient design of sophisticated systems, we present in this paper a novel methodology to create powerful neural network ...
Andreas Huemer, Mario A. Góngora, David A. ...
ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
15 years 10 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
RTAS
2007
IEEE
15 years 10 months ago
An Approach for Real-Time Database Modeling and Performance Management
It is challenging to manage the performance of real-time databases (RTDBs) that are often used in data-intensive real-time applications such as agile manufacturing and target trac...
Jisu Oh, Kyoung-Don Kang