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» Design methodology for IRA codes
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CODES
2000
IEEE
14 years 2 months ago
Parameterized system design
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...
Tony Givargis, Frank Vahid
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
14 years 4 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
CODES
2002
IEEE
14 years 2 months ago
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
This paper considers the problem of designing heterogeneous multiprocessor embedded systems. The focus is on a step of the design flow: the definition of innovative metrics for th...
Donatella Sciuto, Fabio Salice, Luigi Pomante, Wil...
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
14 years 4 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
CODES
2000
IEEE
14 years 2 months ago
Linking codesign and reuse in embedded systems design
This paper presents a complete codesign environment for embedded systems which combines automatic partitioning with reuse from a module database. Special emphasis has been put on ...
Matthias Meerwein, C. Baumgartner, W. Glauert