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» Design of Asynchronous Circuits Using Synchronous CAD Tools
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TVLSI
2002
144views more  TVLSI 2002»
13 years 7 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail
FDL
2011
IEEE
12 years 7 months ago
Integrating system descriptions by clocked guarded actions
—For the description of reactive systems, there is a large number of languages and formalisms, and depending on a particular application or design phase, one of them may be bette...
Jens Brandt, Mike Gemunde, Klaus Schneider, Sandee...
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
13 years 11 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
CDC
2008
IEEE
128views Control Systems» more  CDC 2008»
14 years 1 months ago
Time-robust discrete control over networked Loosely Time-Triggered Architectures
In this paper we consider Loosely Time-Triggered Architectures (LTTA) as a networked infrastructure for deploying discrete control. LTTA are distributed architectures in which 1/ ...
Paul Caspi, Albert Benveniste
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
14 years 1 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu