Sciweavers

351 search results - page 18 / 71
» Design of a WCET-Aware C Compiler
Sort
View
CODES
2006
IEEE
14 years 2 months ago
Retargetable code optimization with SIMD instructions
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...
Manuel Hohenauer, Christoph Schumacher, Rainer Leu...
FM
2003
Springer
107views Formal Methods» more  FM 2003»
14 years 1 months ago
A Formal Framework for Modular Synchronous System Design
We present the formal framework for a novel approach for specifying and automatically implementing systems such as digital circuits and network protocols. The goal is to reduce the...
Maria-Cristina V. Marinescu, Martin C. Rinard
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 2 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
CICLING
2005
Springer
14 years 2 months ago
Design and Development of a System for the Detection of Agreement Errors in Basque
This paper presents the design and development of a system for the detection and correction of syntactic errors in free texts. The system is composed of three main modules: a) a ro...
Arantza Díaz de Ilarraza Sánchez, Ko...
ACSD
2005
IEEE
121views Hardware» more  ACSD 2005»
14 years 2 months ago
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
Matthieu Moy, Florence Maraninchi, Laurent Maillet...