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DATE
2006
IEEE
151views Hardware» more  DATE 2006»
14 years 1 months ago
Designing MRF based error correcting circuits for memory elements
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
14 years 1 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
CEE
2007
105views more  CEE 2007»
13 years 7 months ago
Compact modular exponentiation accelerator for modern FPGA devices
We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of m...
Timo Alho, Panu Hämäläinen, Marko H...
ASYNC
2000
IEEE
181views Hardware» more  ASYNC 2000»
14 years 2 days ago
Asynchronous Design Using Commercial HDL Synthesis Tools
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
Michiel M. Ligthart, Karl Fant, Ross Smith, Alexan...
IPPS
1999
IEEE
13 years 12 months ago
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer
This paper describes a dynamically reconfigurable hardware-based computer called the Plastic Cell Architecture (PCA). PCA consists of dualstructured sea-of -cells that consist of a...
Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Mino...