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POPL
2010
ACM
13 years 10 months ago
Reconfigurable asynchronous logic automata: (RALA)
Computer science has served to insulate programs and programmers from knowledge of the underlying mechanisms used to manipulate information, however this fiction is increasingly h...
Neil Gershenfeld, David Dalrymple, Kailiang Chen, ...
DAC
2005
ACM
14 years 8 months ago
Incremental retiming for FPGA physical synthesis
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
Deshanand P. Singh, Valavan Manohararajah, Stephen...
IWANN
2005
Springer
14 years 1 months ago
An Asynchronous 4-to-4 AER Mapper
In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol original...
Håvard Kolle Riis, Philipp Häfliger
FPGA
2009
ACM
273views FPGA» more  FPGA 2009»
14 years 2 months ago
A parallel/vectorized double-precision exponential core to accelerate computational science applications
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
Robin Pottathuparambil, Ron Sass
TVLSI
2008
119views more  TVLSI 2008»
13 years 7 months ago
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Katherine Compton, Scott Hauck