58 search results - page 7 / 12 » Design of a scalable nanophotonic interconnect for future mu... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
SPAA
2010
ACM
14 years 12 days ago
2010
ACM
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path b...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ISCAPDCS
2004
13 years 9 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...