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IEEEPACT
2000
IEEE
15 years 8 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
IPPS
2000
IEEE
15 years 8 months ago
Monotonic Counters: A New Mechanism for Thread Synchronization
Only a handful of fundamental mechanisms for synchronizing the access of concurrent threads to shared memory are widely implemented and used. These include locks, condition variab...
John Thornley, K. Mani Chandy
ISORC
2000
IEEE
15 years 8 months ago
An Open QoS Architecture for CORBA Applications
Distributed application programmers rely on middleware such as CORBA in order to handle the complexity that arises from the distributed and heterogeneous nature of the underlying ...
Frank Siqueira, Vinny Cahill
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
15 years 8 months ago
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
Li Chen, Sujit Dey
115
Voted
ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
15 years 8 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino