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» Design space exploration of caches using compressed traces
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ICS
2004
Tsinghua U.
14 years 24 days ago
Design space exploration of caches using compressed traces
Xianfeng Li, Hemendra Singh Negi, Tulika Mitra, Ab...
CODES
2008
IEEE
14 years 1 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
13 years 11 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
AINA
2007
IEEE
14 years 1 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 7 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana