Sciweavers

168 search results - page 11 / 34
» Design with race-free hardware semantics
Sort
View
ICECCS
2005
IEEE
125views Hardware» more  ICECCS 2005»
14 years 1 months ago
Model Checking Live Sequence Charts
Live Sequence Charts (LSCs) are a broad extension to Message Sequence Charts (MSCs) to capture complex interobject communication rigorously. A tool support for LSCs, named PlayEng...
Jun Sun 0001, Jin Song Dong
ACSD
2005
IEEE
121views Hardware» more  ACSD 2005»
14 years 1 months ago
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
Matthieu Moy, Florence Maraninchi, Laurent Maillet...
MEMOCODE
2010
IEEE
13 years 5 months ago
A formal executable semantics of Verilog
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
Patrick O'Neil Meredith, Michael Katelman, Jos&eac...
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 2 months ago
Componentizing hardware/software interface design
Abstract—Building highly optimized embedded systems demands hardware/software (HW/SW) co-design. A key challenge in co-design is the design of HW/SW interfaces, which is often a ...
Kecheng Hao, Fei Xie
CCR
2006
92views more  CCR 2006»
13 years 7 months ago
Flow labelled IP over ATM: design and rationale
We describe a system in which layer 2 switching is placed directly under the control of layer 3 routing protocols on a hop-by-hop basis. Specifically, ATM switching is controlled ...
Greg Minshall, Robert M. Hinden, Eric Hoffman, Fon...