Sciweavers

397 search results - page 52 / 80
» Designing Fast Asynchronous Circuits
Sort
View
IANDC
2010
84views more  IANDC 2010»
13 years 6 months ago
Underapproximation for model-checking based on universal circuits
For two naturals m, n such that m < n, we show how to construct a circuit C with m inputs and n outputs, that has the following property: for some 0 ≤ k ≤ m, the circuit deï...
Arie Matsliah, Ofer Strichman
DAC
2000
ACM
14 years 8 months ago
MINFLOTRANSIT: min-cost flow based transistor sizing tool
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
14 years 1 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
Fast wire length estimation by net bundling for block placement
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
Tan Yan, Hiroshi Murata
ASPDAC
2007
ACM
86views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Fast Buffered Delay Estimation Considering Process Variations
- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations...
Tien-Ting Fang, Ting-Chi Wang