Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacc...
We consider the model of unreliable network links, where at each time unit a link might be either up or down. We consider two related problems. The first, establishing end to end...
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
Federico Angiolini, David Atienza, Srinivasan Mura...
This paper presents a design and analysis of scheduling techniques to cope with the inherent unreliability and instability of worker nodes in large-scale donation-based distribute...
Jason D. Sonnek, Mukesh Nathan, Abhishek Chandra, ...