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LCTRTS
2010
Springer
13 years 8 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
POPL
2012
ACM
12 years 5 months ago
Static and user-extensible proof checking
Despite recent successes, large-scale proof development within proof assistants remains an arcane art that is extremely timeconsuming. We argue that this can be attributed to two ...
Antonis Stampoulis, Zhong Shao
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 4 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
MIDDLEWARE
2004
Springer
14 years 3 months ago
iOverlay: A Lightweight Middleware Infrastructure for Overlay Application Implementations
The very nature of implementing and evaluating fully distributed algorithms or protocols in application-layer overlay networks involves certain programming tasks that are at best m...
Baochun Li, Jiang Guo, Mea Wang
ASPLOS
1989
ACM
14 years 2 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....