2945 search results - page 101 / 589 » Designing and Implementing Malicious Hardware |
139
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
143
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FPL
2009
Springer
15 years 9 months ago
2009
Springer
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
186
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FPL
2006
Springer
15 years 8 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
133
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DFT
2003
IEEE
15 years 9 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
131
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...