2945 search results - page 451 / 589 » Designing and Implementing Malicious Hardware |
166
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
150
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
153
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
In order to enable face animation on the Internet using high quality synthetic speech, the Text-to-Speech (TTS) servers need to be implemented on network-based servers and shared ...
154
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SIGMETRICS
2010
ACM
15 years 11 months ago
2010
ACM
We present RSIO, a processor scheduling framework for improving the response time of latency-sensitive applications by monitoring accesses to I/O channels and inferring when user ...
182
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ECMDAFA
2010
Springer
15 years 11 months ago
2010
Springer
Use cases are commonly used to structure and document requirements while UML activity diagrams are often used to visualize and formalize use cases, for example to support automated...