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SPAA
2010
ACM
15 years 9 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
EVOW
2006
Springer
15 years 8 months ago
Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm
Abstract. The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Prev...
Andrew Kinane, Valentin Muresan, Noel E. O'Connor
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
15 years 8 months ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
ANNPR
2006
Springer
15 years 6 months ago
A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware
Abstract. Recently, the authors described a training method for a convolutional neural network of threshold neurons. Hidden layers are trained by by clustering, in a feed-forward m...
Johannes Fieres, Karlheinz Meier, Johannes Schemme...
IJNSEC
2008
106views more  IJNSEC 2008»
15 years 4 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...