Sciweavers

1421 search results - page 86 / 285
» Designing system on a chip products using systems engineerin...
Sort
View
CODES
2007
IEEE
14 years 3 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
IPPS
2003
IEEE
14 years 2 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
SP
2010
IEEE
226views Security Privacy» more  SP 2010»
14 years 23 days ago
Chip and PIN is Broken
—EMV is the dominant protocol used for smart card payments worldwide, with over 730 million cards in circulation. Known to bank customers as “Chip and PIN”, it is used in Eur...
Steven J. Murdoch, Saar Drimer, Ross J. Anderson, ...
FASE
2000
Springer
14 years 15 days ago
More About TAS and IsaWin - Tools for Formal Program Development
We present a family of tools for program development and verification, comprising the transformation system TAS and the theorem proving interface IsaWin. Both are based on the theo...
Christoph Lüth, Burkhart Wolff
INFSOF
2007
81views more  INFSOF 2007»
13 years 8 months ago
An infrastructure to support interoperability in reverse engineering
An infrastructure is a set of interconnected structural elements, such as tools and schemas, that provide a framework for supporting an entire structure. The reverse engineering c...
Nicholas A. Kraft, Brian A. Malloy, James F. Power