The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Background: One of the essential processing events during pre-mRNA maturation is the posttranscriptional addition of a polyadenine [poly(A)] tail. The 3'-end poly(A) track pr...
Guoli Ji, Jianti Zheng, Yingjia Shen, Xiaohui Wu, ...
Background: In expressed sequence tag (EST) sequencing, we are often interested in how many genes we can capture in an EST sample of a targeted size. This information provides ins...
Ji-Ping Z. Wang, Bruce G. Lindsay 0002, Liying Cui...