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MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
14 years 1 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
TWC
2008
154views more  TWC 2008»
13 years 7 months ago
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...
Sofie Pollin, Rahul Mangharam, Bruno Bougard, Lies...
CF
2006
ACM
14 years 1 months ago
Tile size selection for low-power tile-based architectures
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...
John Oliver, Ravishankar Rao, Michael Brown, Jenni...
ICC
2007
IEEE
118views Communications» more  ICC 2007»
14 years 1 months ago
Sending Correlated Gaussian Sources over a Gaussian MAC: To Code, or not to Code
— We consider 1-helper problem in which one source provides partial side information to the fusion center (FC) to help reconstruction of the main source signal. Both sources comm...
Hamid Behroozi, M. Reza Soleymani
DSN
2002
IEEE
14 years 14 days ago
Ditto Processor
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir