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» DiProNN: Distributed Programmable Network Node Architecture
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ICPP
1999
IEEE
13 years 12 months ago
The Index-Permutation Graph Model for Hierarchical Interconnection Networks
In this paper, we present the index-permutation (IP) graph model, and apply it to the systematic development of efficient hierarchical networks. We derive several classes of inter...
Chi-Hsiang Yeh, Behrooz Parhami
SENSYS
2005
ACM
14 years 1 months ago
TSAR: a two tier sensor storage architecture using interval skip graphs
Archival storage of sensor data is necessary for applications that query, mine, and analyze such data for interesting features and trends. We argue that existing storage systems a...
Peter Desnoyers, Deepak Ganesan, Prashant J. Sheno...
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 1 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
PODC
2009
ACM
14 years 8 months ago
Bounding the locality of distributed routing algorithms
d Abstract] Prosenjit Bose School of Computer Science Carleton University Ottawa, Canada jit@scs.carleton.ca Paz Carmi Dept. of Computer Science Ben-Gurion Univ. of the Negev Beer-...
Prosenjit Bose, Paz Carmi, Stephane Durocher
IPPS
1995
IEEE
13 years 11 months ago
Operating system support for concurrent remote task creation
This paper describes improvements to the Mach microkernel’s support for efficient application startup across multiple nodes in a cluster or massively parallel processor. Signifi...
Dejan S. Milojicic, David L. Black, Steven J. Sear...