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ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 9 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
IPL
2000
76views more  IPL 2000»
13 years 8 months ago
Deterministic small-world communication networks
Many real life networks, including the World Wide Web, electric power grids, and social networks, are small-world networks. The two distinguishing characteristics of small-world n...
Francesc Comellas, Javier Ozón, Joseph G. P...
JSA
2006
86views more  JSA 2006»
13 years 8 months ago
High-performance adaptive routing for networks with arbitrary topology
A strategy to implement adaptive routing in irregular networks is presented and analyzed in this work. A simple and widely applicable deadlock avoidance method, applied to a ring ...
Valentin Puente, José A. Gregorio, Fernando...
SSPR
2004
Springer
14 years 1 months ago
Structures of Covariance Matrix in Handwritten Character Recognition
The integrated approach is a classifier established on statistical estimator and artificial neural network. This consists of preliminary data whitening transformation which provide...
Sarunas Raudys, Masakazu Iwamura
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
13 years 6 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan