Sciweavers

162 search results - page 25 / 33
» Diagnosis Strategies for Hardware or Software Systems
Sort
View
IEEEPACT
2006
IEEE
14 years 1 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
LCTRTS
1998
Springer
13 years 11 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
UIST
2010
ACM
13 years 5 months ago
Madgets: actuating widgets on interactive tabletops
We present a system for the actuation of tangible magnetic widgets (Madgets) on interactive tabletops. Our system combines electromagnetic actuation with fiber optic tracking to m...
Malte Weiss, Florian Schwarz, Simon Jakubowski, Ja...
ISPASS
2003
IEEE
14 years 22 days ago
Performance analysis and optimization of a distributed Video on Demand service
Video on Demand (VoD) services are very appealing these days. In this work, we discuss four distinct alternatives for the architecture of a VoD server and compare their performanc...
Daniela Alvim Seabra dos Santos, Alex Borges Vieir...
LCTRTS
1999
Springer
13 years 11 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...