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» Diagonal routing in high performance microprocessor design
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CF
2005
ACM
13 years 10 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
INFOCOM
2009
IEEE
14 years 3 months ago
Visibility-Graph-Based Shortest-Path Geographic Routing in Sensor Networks
— We study the problem of shortest-path geographic routing in a static sensor network. Existing algorithms often make routing decisions based on node information in local neighbo...
Guang Tan, Marin Bertier, Anne-Marie Kermarrec
ITCC
2005
IEEE
14 years 2 months ago
Zonal Rumor Routing for Wireless Sensor Networks
has to be relayed to nodes interested in those events. Moreover, nodes may also generate queries to find events they are interested in. Thus there is a need to route the informatio...
Tarun Banka, Gagan Tandon, Anura P. Jayasumana
HPCA
2000
IEEE
14 years 27 days ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
MONET
2007
126views more  MONET 2007»
13 years 8 months ago
Performance Evaluation of a Power Management Scheme for Disruption Tolerant Network
Disruption Tolerant Network (DTN) is characterized by frequent partitions and intermittent connectivity. Power management issue in such networks is challenging. Existing power man...
Yong Xi, Mooi Choo Chuah, K. Chang