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» Diagonal routing in high performance microprocessor design
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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 1 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
FOCS
1997
IEEE
13 years 11 months ago
General Dynamic Routing with Per-Packet Delay Guarantees of O(distance + 1 / session rate)
A central issue in the design of modern communication networks is that of providing performance guarantees. This issue is particularly important if the networks support real-time t...
Matthew Andrews, Antonio Fernández, Mor Har...
LCTRTS
2010
Springer
14 years 2 months ago
Modeling structured event streams in system level performance analysis
This paper extends the methodology of analytic real-time analysis of distributed embedded systems towards merging and extracting sub-streams based on event type information. For e...
Simon Perathoner, Tobias Rein, Lothar Thiele, Kai ...
CASES
2003
ACM
14 years 20 days ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 10 days ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith