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DELTA
2002
IEEE
14 years 2 months ago
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-...
Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
ISQED
2002
IEEE
111views Hardware» more  ISQED 2002»
14 years 2 months ago
Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)
The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity ...
Mandeep Singh, Israel Koren
ICES
2007
Springer
83views Hardware» more  ICES 2007»
14 years 3 months ago
Extrinsic Evolvable Hardware on the RISA Architecture
The RISA Architecture is a novel reconfigurable hardware platform containing both hardware and software reconfigurable elements. This paper describes the architecture and the fea...
Andrew J. Greensted, Andrew M. Tyrrell
EH
2003
IEEE
129views Hardware» more  EH 2003»
14 years 2 months ago
The Importance of Reuse and Development in Evolvable Hardware
Reuse will become increasingly important as larger digital and analog circuits are created by the techniques of the field of evolvable hardware. This paper discusses the ways by w...
John R. Koza, Martin A. Keane, Matthew J. Streeter
ASAP
1997
IEEE
106views Hardware» more  ASAP 1997»
14 years 1 months ago
Libraries of schedule-free operators in Alpha
This paper presents a method, based on the formalism of affine recurrence equations, for the synthesis of digital circuits exploiting parallelism at the bit-level. In the initial ...
Florent de Dinechin