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ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
14 years 1 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
CHARME
1995
Springer
120views Hardware» more  CHARME 1995»
14 years 17 days ago
Timing analysis of asynchronous circuits using timed automata
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
Oded Maler, Amir Pnueli
COCO
2008
Springer
100views Algorithms» more  COCO 2008»
13 years 10 months ago
Detecting Rational Points on Hypersurfaces over Finite Fields
We study the complexity of deciding whether a given homogeneous multivariate polynomial has a nontrivial root over a finite field. Given a homogeneous algebraic circuit C that com...
Swastik Kopparty, Sergey Yekhanin
TCS
2008
13 years 9 months ago
Turing machines and bimachines
We associate the iterated block product of a bimachine with a deterministic Turing machine. This allows us to introduce new algebraic notions to study the behavior of the Turing m...
John Rhodes, Pedro V. Silva
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 9 months ago
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit C...