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DATE
2009
IEEE
107views Hardware» more  DATE 2009»
13 years 11 months ago
Sequential logic rectifications with approximate SPFDs
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, R...
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
KES
2008
Springer
13 years 7 months ago
Incremental evolution of a signal classification hardware architecture for prosthetic hand control
Evolvable Hardware (EHW) is a new method for designing electronic circuits. However, there are several problems to solve for making high performance systems. One is the limited sca...
Jim Torresen
SIAMCOMP
2000
66views more  SIAMCOMP 2000»
13 years 7 months ago
Computations of Uniform Recurrence Equations Using Minimal Memory Size
We consider a system of uniform recurrence equations (URE) of dimension one. We show how its computation can be carried out using minimal memory size with several synchronous proc...
Bruno Gaujal, Alain Jean-Marie, Jean Mairesse
ECCTD
2011
72views more  ECCTD 2011»
12 years 7 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic