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CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
SIGCOMM
2009
ACM
14 years 2 months ago
SMACK: a SMart ACKnowledgment scheme for broadcast messages in wireless networks
Network protocol designers, both at the physical and network level, have long considered interference and simultaneous transmission in wireless protocols as a problem to be avoide...
Aveek Dutta, Dola Saha, Dirk Grunwald, Douglas C. ...
PVM
2010
Springer
13 years 5 months ago
Toward Performance Models of MPI Implementations for Understanding Application Scaling Issues
Abstract. Designing and tuning parallel applications with MPI, particularly at large scale, requires understanding the performance implications of different choices of algorithms ...
Torsten Hoefler, William Gropp, Rajeev Thakur, Jes...
ACSD
2006
IEEE
129views Hardware» more  ACSD 2006»
14 years 1 months ago
Communicating with Synchronized Environments
In the modern design environments, different modules, available in existent libraries, may obey different architectural styles and execution models. Reaching a well– behaved com...
Tiberiu Seceleanu, Axel Jantsch
FPL
2001
Springer
96views Hardware» more  FPL 2001»
13 years 12 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...