Sciweavers

3006 search results - page 567 / 602
» Dimensionality reduction and generalization
Sort
View
GLVLSI
2008
IEEE
129views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Variational capacitance modeling using orthogonal polynomial method
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...
Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X....
IEEEPACT
2008
IEEE
14 years 2 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
CODES
2007
IEEE
14 years 2 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
CODES
2007
IEEE
14 years 2 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
INFOCOM
2007
IEEE
14 years 2 months ago
Routing with a Markovian Metric to Promote Local Mixing
— Routing protocols have traditionally been based on finding shortest paths under certain cost metrics. A conventional routing metric models the cost of a path as the sum of the...
Yunnan Wu, Saumitra M. Das, Ranveer Chandra