Sciweavers

315 search results - page 58 / 63
» Disk layout optimization for reducing energy consumption
Sort
View
CODES
2006
IEEE
14 years 1 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
DAC
2009
ACM
14 years 8 months ago
Power modeling of graphical user interfaces on OLED displays
Emerging organic light-emitting diode (OLED)-based displays obviate external lighting; and consume drastically different power when displaying different colors, due to their emiss...
Mian Dong, Yung-Seok Kevin Choi, Lin Zhong
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 7 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
HICSS
2009
IEEE
155views Biometrics» more  HICSS 2009»
14 years 2 months ago
Collaborative Recommender Systems for Building Automation
Building Automation Systems (BASs) can save building owners money by reducing energy consumption while simultaneously preserving occupant comfort. There are algorithms that optimi...
Michael LeMay, Jason J. Haas, Carl A. Gunter
ECRTS
2007
IEEE
14 years 1 months ago
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
Jean-François Deverge, Isabelle Puaut