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ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
14 years 23 days ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong
BMCBI
2004
138views more  BMCBI 2004»
13 years 8 months ago
Constraint Logic Programming approach to protein structure prediction
Background: The protein structure prediction problem is one of the most challenging problems in biological sciences. Many approaches have been proposed using database information ...
Alessandro Dal Palù, Agostino Dovier, Feder...
JAR
2007
132views more  JAR 2007»
13 years 8 months ago
Visualizing SAT Instances and Runs of the DPLL Algorithm
SAT-solvers have turned into essential tools in many areas of applied logic like, for example, hardware verification or satisfiability checking modulo theories (SMT). And althoug...
Carsten Sinz
PAMI
2006
135views more  PAMI 2006»
13 years 8 months ago
Real-Time Range Acquisition by Adaptive Structured Light
The goal of this paper is to provide a "self-adaptive" system for real-time range acquisition. Reconstructions are based on a single frame structured light illumination. ...
Thomas P. Koninckx, Luc J. Van Gool
GECCO
2008
Springer
103views Optimization» more  GECCO 2008»
13 years 9 months ago
Empirical investigations on parallel competent genetic algorithms
This paper empirically investigates parallel competent genetic algorithms (cGAs) [4]. cGAs, such as BOA [21], LINCGA [15], D5 -GA [28], can solve GA-difficult problems by automati...
Miwako Tsuji, Masaharu Munetomo, Kiyoshi Akama