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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 5 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
CRIWG
2004
13 years 8 months ago
A Decoupled Architecture for Action-Oriented Coordination and Awareness Management in CSCL/W Frameworks
This paper introduces AORTA, a software architecture that provides object-level coordination and shared workspace awareness support to synchronous and distributed collaborative app...
Pablo Orozco, Juan I. Asensio-Pérez, Pedro ...
EUROSYS
2007
ACM
14 years 3 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek
SIGSOFT
2008
ACM
14 years 7 months ago
Towards compositional synthesis of evolving systems
Synthesis of system configurations from a given set of features is an important and very challenging problem. This paper makes a step towards this goal by describing an efficient ...
Shiva Nejati, Mehrdad Sabetzadeh, Marsha Chechik, ...
FPGA
2009
ACM
285views FPGA» more  FPGA 2009»
14 years 1 months ago
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from the ClamAV virus signature database in a data stream. This paper presents PERG...
Johnny Tsung Lin Ho, Guy G. Lemieux