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HPCA
2008
IEEE
14 years 8 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
CAL
2010
13 years 5 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
SIGCOMM
2009
ACM
14 years 2 months ago
A programmable overlay router for service provider innovation
The threat of commoditization poses a real challenge for service providers. While the end-to-end principle is often paraphrased as “dumb network, smart end-systems”, the origi...
Bruce S. Davie, Jan Medved
ARCS
2006
Springer
13 years 11 months ago
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter
As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss i...
Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien...
ANCS
2009
ACM
13 years 5 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve...