Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
I/O bottlenecks are already a problem in many largescale applications that manipulate huge datasets. This problem is expected to get worse as applications get larger, and the I/O ...
Murali Vilayannur, Anand Sivasubramaniam, Mahmut T...