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109
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ICS
1998
Tsinghua U.
15 years 6 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
109
Voted
ICPP
1994
IEEE
15 years 6 months ago
Cachier: A Tool for Automatically Inserting CICO Annotations
Shared memory in a parallel computer provides prowith the valuable abstraction of a shared address space--through which any part of a computation can access any datum. Although un...
Trishul M. Chilimbi, James R. Larus
148
Voted
EDCC
2006
Springer
15 years 6 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
145
Voted
USENIX
1994
15 years 3 months ago
Reducing File System Latency using a Predictive Approach
Despite impressive advances in file system throughput resulting from technologies such as high-bandwidth networks and disk arrays, file system latency has not improved and in many...
Jim Griffioen, Randy Appleton
JPDC
2006
133views more  JPDC 2006»
15 years 2 months ago
Locality in structured peer-to-peer networks
Distributed hash tables (DHTs), used in a number of structured peer-to-peer (P2P) systems provide efficient mechanisms for resource placement and location. A key distinguishing fe...
Ronaldo A. Ferreira, Suresh Jagannathan, Ananth Gr...