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IPPS
2010
IEEE
15 years 10 days ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
126
Voted
IEEEPACT
2009
IEEE
15 years 4 days ago
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
Carlos Luque, Miquel Moretó, Francisco J. C...
133
Voted
HPCA
2011
IEEE
14 years 6 months ago
Calvin: Deterministic or not? Free will to choose
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
Derek Hower, Polina Dudnik, Mark D. Hill, David A....
PAM
2010
Springer
15 years 9 months ago
MOR: Monitoring and Measurements through the Onion Router
Abstract. A free and easy to use distributed monitoring and measurement platform would be valuable in several applications: monitoring network or server infrastructures, performing...
Demetres Antoniades, Evangelos P. Markatos, Consta...
110
Voted
ICPPW
2009
IEEE
15 years 9 months ago
Towards a Component-Based Observation of MPSoC
Abstract——Motivated by the increasing heterogeneity and complexity of MPSoC systems, we propose a component-based generic approach for MPSoC observation. We show that components...
Carlos Prada-Rojas, Vania Marangozova-Martin, Kiri...