Sciweavers

767 search results - page 52 / 154
» Distributed Queueing in Scalable High Performance Routers
Sort
View
CONNECTION
2007
87views more  CONNECTION 2007»
13 years 8 months ago
Efficient architectures for sparsely-connected high capacity associative memory models
In physical implementations of associative memory, wiring costs play a significant role in shaping patterns of connectivity. In this study of sparsely-connected associative memory...
Lee Calcraft, Rod Adams, Neil Davey
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
13 years 12 days ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
SPAA
2010
ACM
14 years 1 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
ICS
1999
Tsinghua U.
14 years 29 days ago
Performance impact of proxies in data intensive client-server applications
Large client-server data intensive applications can place high demands on system and network resources. This is especially true when the connection between the client and server s...
Michael D. Beynon, Alan Sussman, Joel H. Saltz
CCGRID
2008
IEEE
14 years 3 months ago
Optimized Distributed Data Sharing Substrate in Multi-core Commodity Clusters: A Comprehensive Study with Applications
Distributed applications tend to have a complex design due to issues such as concurrency, synchronization and communication. Researchers in the past have proposed abstractions to ...
Karthikeyan Vaidyanathan, Ping Lai, Sundeep Narrav...