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ISVLSI
2003
IEEE
138views VLSI» more  ISVLSI 2003»
14 years 3 months ago
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
Sarah E. Frost, Arun Rodrigues, Charles A. Giefer,...
CONCUR
2011
Springer
12 years 9 months ago
Reasoning about Threads with Bounded Lock Chains
The problem of model checking threads interacting purely via the standard synchronization primitives is key for many concurrent program analyses, particularly dataflow analysis. U...
Vineet Kahlon
RTSS
2005
IEEE
14 years 3 months ago
Preemptible Atomic Regions for Real-Time Java
nt a new concurrency control abstraction for real-time systems called preemptible atomic regions (PARs). PARs a transactional mechanism that improves upon lock-based mutual exclus...
Jeremy Manson, Jason Baker, Antonio Cunei, Suresh ...
OOPSLA
1999
Springer
14 years 2 months ago
Compositional Pointer and Escape Analysis for Java Programs
This paper presents a combined pointer and escape analysis algorithm for Java programs. The algorithm is based on the abstraction of points-to escape graphs, which characterize ho...
John Whaley, Martin C. Rinard
ICPP
2003
IEEE
14 years 3 months ago
Data Conversion for Process/Thread Migration and Checkpointing
Process/thread migration and checkpointing schemes support load balancing, load sharing and fault tolerance to improve application performance and system resource usage on worksta...
Hai Jiang, Vipin Chaudhary, John Paul Walters