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CGO
2004
IEEE
14 years 26 days ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
TVLSI
2008
150views more  TVLSI 2008»
13 years 8 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
PDP
2002
IEEE
14 years 2 months ago
A Parametrized Algorithm that Implements Sequential, Causal, and Cache Memory Consistency
In this paper we present an algorithm that can be used to implement sequential, causal, or cache consistency in distributed shared memory (DSM) systems. For this purpose it has a ...
Ernesto Jiménez, Antonio Fernández, ...
INFOSCALE
2007
ACM
13 years 10 months ago
Load-balancing and caching for collection selection architectures
— To address the rapid growth of the Internet, modern Web search engines have to adopt distributed organizations, where the collection of indexed documents is partitioned among s...
Diego Puppin, Fabrizio Silvestri, Raffaele Perego,...
ICRA
2008
IEEE
145views Robotics» more  ICRA 2008»
14 years 3 months ago
Cooperative anchoring in heterogeneous multi-robot systems
Abstract— Highly heterogeneous robotic systems are becoming increasingly common, as are robotic systems integrated with smart environments. In such distributed systems, there are...
Kevin LeBlanc, Alessandro Saffiotti