Sciweavers

71 search results - page 6 / 15
» Distributing processing without DPEs: design considerations ...
Sort
View
145
Voted
HPCA
2011
IEEE
14 years 7 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
132
Voted
IPPS
2007
IEEE
15 years 10 months ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel
DAC
2002
ACM
16 years 4 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
189
Voted
JCDL
2011
ACM
301views Education» more  JCDL 2011»
14 years 6 months ago
Archiving the web using page changes patterns: a case study
A pattern is a model or a template used to summarize and describe the behavior (or the trend) of a data having generally some recurrent events. Patterns have received a considerab...
Myriam Ben Saad, Stéphane Gançarski
150
Voted
ASPLOS
1987
ACM
15 years 7 months ago
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures
This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting...
Richard F. Rashid, Avadis Tevanian, Michael Young,...