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ISVLSI
2002
IEEE
81views VLSI» more  ISVLSI 2002»
14 years 3 months ago
Impact of Technology Scaling in the Clock System Power
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
DAC
1997
ACM
14 years 2 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
TWC
2008
124views more  TWC 2008»
13 years 10 months ago
Reverse Link Performance of a DS-CDMA System With Both Fast and Slow Power Controlled Users
In this paper the performance of the reverse link of a multicell DS-CDMA system with coexisting open-loop and closed-loop power controlled users transmitting heterogeneous traffic ...
Loren Carrasco, Guillem Femenias
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
14 years 4 months ago
Quasi-Resonant Interconnects: A Low Power Design Methodology
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
Jonathan Rosenfeld, Eby G. Friedman
SOCA
2007
IEEE
14 years 4 months ago
VIDIHIP - A Web Service based Integration Platform for Power Plant Control Systems
European energy supply companies typically run a conglomerate of different, geographically distributed power plants. Unfortunately, the corresponding power plant control systems a...
Mark Strembeck, Otto U. Plhal