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PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 2 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
ITRE
2005
IEEE
14 years 2 months ago
MR-FQ: a fair scheduling algorithm for wireless networks with variable transmission rates
— Wireless networks are characterized by bursty and location-dependent errors. Although many fair scheduling methods have been proposed to address these issues, most of them assu...
You-Chiun Wang, Yu-Chee Tseng, Wen-Tsuen Chen, Kun...
CHI
2009
ACM
14 years 9 months ago
Design and adoption of social collaboration software within businesses
Social networking and collaboration sites are having a large impact on people's personal lives. These same applications, similar functions and related experiences are being a...
Jason Blackwell, John Sheridan, Keith Instone, Dav...
AGILEDC
2007
IEEE
14 years 3 months ago
A Strategy for Balancing Business Value and Story Size
What would your Analyst team do when torn between meeting Customer versus Developer demands? When their needs conflict with one another, how do you appease them both? The report o...
Hai Ton
GLOBECOM
2007
IEEE
14 years 15 days ago
Mean-Field Analysis of Buffer Sizing
Two schools of thoughts have emerged over the recent debate on internet router buffer sizing. One school argues that the presence of a large number of flows leads to traffic desync...
Mei Wang