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INFOCOM
2002
IEEE
15 years 7 months ago
Clock Synchronization Algorithms for Network Measurements
Abstract—Packet delay traces are important measurements for analyzing end-to-end performance and for designing traffic control algorithms in computer networks. Due to the fact t...
Li Zhang, Zhen Liu, Cathy H. Xia
113
Voted
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 7 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
LION
2010
Springer
209views Optimization» more  LION 2010»
15 years 7 months ago
Feature Extraction from Optimization Data via DataModeler's Ensemble Symbolic Regression
We demonstrate a means of knowledge discovery through feature extraction that exploits the search history of an optimization run. We regress a symbolic model ensemble from optimiza...
Kalyan Veeramachaneni, Katya Vladislavleva, Una-Ma...
136
Voted
MOBILITY
2009
ACM
15 years 7 months ago
Context adaptative systems based on horizontal architecture for ubiquitous computing
Many adaptative context-aware middleware exist and mostly rely on so-called vertical architectures that offer a functional decomposition for context-awareness. This architecture ...
Nicolas Ferry, Stephane Lavirotte, Jean-Yves Tigli...
106
Voted
FPL
2009
Springer
99views Hardware» more  FPL 2009»
15 years 7 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne