90 search results - page 17 / 18 » Dynamic Branch Prediction with Perceptrons |
ICS
1998
Tsinghua U.
13 years 12 months ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
BSN
2009
IEEE
14 years 2 months ago
2009
IEEE
— This article describes an approach to detecting mental stress using unobtrusive wearable sensors. The approach relies on estimating the state of the autonomic nervous system fr...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that ...
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...