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ERSA
2006
100views Hardware» more  ERSA 2006»
13 years 8 months ago
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Markus Koester, Heiko Kalte, Mario Porrmann
CODES
2003
IEEE
14 years 21 days ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
14 years 1 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
EMSOFT
2010
Springer
13 years 5 months ago
Energy-aware packet and task co-scheduling for embedded systems
A crucial objective in battery operated embedded systems is to work under the minimal power consumption that provides a desired level of performance. Dynamic Voltage Scaling (DVS)...
Luca Santinelli, Mauro Marinoni, Francesco Prosper...
VLDB
2000
ACM
166views Database» more  VLDB 2000»
13 years 11 months ago
High-Performance and Scalability through Application Tier,In-Memory Data Management
TimesTen Performance Software's Front-Tier product is an application-tier data cache that inter-operates with disk-based relational database management systems (RDBMSs) to ac...