69 search results - page 5 / 14 » Dynamic Fetch Engine for Simultaneous Multithreaded Processo... |
HPCA
1999
IEEE
14 years 22 days ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
CGO
2004
IEEE
14 years 5 days ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ISPASS
2006
IEEE
14 years 2 months ago
2006
IEEE
Commercial processors have support for Simultaneous Multithreading (SMT), yet little work has been done to provide representative simulation results for SMT. Given a workload, cur...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...