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HPCA
2005
IEEE
14 years 9 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
CADE
2001
Springer
14 years 9 months ago
More On Implicit Syntax
Proof assistants based on type theories, such as Coq and Lego, allow users to omit subterms on input that can be inferred automatically. While those mechanisms are well known, ad-h...
Marko Luther
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 6 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
DAC
2009
ACM
14 years 3 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ERSHOV
2009
Springer
14 years 3 months ago
Towards a Scalable, Pragmatic Knowledge Representation Language for the Web
Abstract. A basic cornerstone of the Semantic Web are formal languages for describing resources in a clear and unambiguous way. Logical underpinnings facilitate automated reasoning...
Florian Fischer, Gulay Ünel, Barry Bishop, Di...
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