—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthe...
Dynamic Topological Logic provides a context for studying the confluence of the topological semantics for S4, based on topological spaces rather than Kripke frames; topological dy...
The paper presents an unified Description Logic (DL) model for databases. Describing database models using DLs is a fundamental problem in many areas because it turns databases to...