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» Dynamic Memory Design for Low Data-Retention Power
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ASPLOS
2012
ACM
12 years 4 months ago
Architecture support for disciplined approximate programming
Disciplined approximate programming lets programmers declare which parts of a program can be computed approximately and consequently at a lower energy cost. The compiler proves st...
Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug...
MONET
2011
13 years 3 months ago
iDSRT: Integrated Dynamic Soft Real-time Architecture for Critical Infrastructure Data Delivery over WLAN
Critical Infrastructures (CIs) such as the Power Grid play an important role in our lives. Of all important aspects of CIs, real-time data delivery is the most important one becaus...
Hoang Viet Nguyen, Raoul Rivas, Klara Nahrstedt
TCAD
2010
97views more  TCAD 2010»
13 years 3 months ago
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
ASPLOS
2012
ACM
12 years 4 months ago
A case for unlimited watchpoints
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...
Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd ...
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 3 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...